LM3528TMXSLASHNOPB datasheet(28/34 Pages) TI1

28 / 34 page

LM3528

SNVS513B – AUGUST 2008 – REVISED MAY 2013

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4. Connect the inductor on the top layer close to the SW pin. There should be a low impedance connection from

the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the SW node

should be small so as to reduce the capacitive coupling of the high dV/dt present at SW that can couple into

nearby traces.

5. , Route the traces for RSET and the feedback divider away from the SW node to minimize the capacitance

between these nodes that can couple the high dV/dt present at SW into them. Furthermore, the feedback divider

and RSETshould have dedicated returns that terminate directly to the PGND pin of the device. This will minimize

any shared current with COUT or CIN that can lead to instability. Avoide routing the SUB/FB node close to other

traces that can see high dV/dt such as the I2C pins. The capacitive coupling on the PCB between FB and these

nodes can disturb the output voltage and cause large voltage spikes at VOUT.

6. Do not connect any external capacitance to the SET pin.

7. Refer to the LM3528 Evaluation Board as a guide for proper layout.

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LM3528TMX/NOPB Datasheet(PDF) 28 Page - Texas Instruments