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High-Z

EN

IN

Y:/1

Undefined

Low

High-Z

Y:/2

Undefined

Low

High-Z

Y:/4

Undefined

Low

1

µs

Signal State After the Device is Enabled (IN = Low)

High-Z

EN

IN

Y:/1

Undefined

Low

High-Z

Y:/2

Undefined

Low

High-Z

Y:/4

Undefined

Low

1

µs

Signal State After the Device is Enabled (IN = High)

Undivided State is Valid After the First

Positive Transition of the Input Clock

T0068-01

Enabling a Single Output Stage

CDCM1804

SCAS697E – JULY 2003 – REVISED MAY 2005

APPLICATION INFORMATION (continued)

Figure 15. Waveforms

If a single output stage becomes enabled:

•

Y[2:0] is either low or high (undefined).

•

Y[2:0] is the inverted signal of Y[2:0].

With the first positive clock transition, the undivided output becomes the input clock state. The divided output

states are equal to the actual internal divider. The internal divider is not reset while enabling single-output drivers.

17