CPC5601D datasheet(11/15 Pages) IXYS

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INTEGRATED CIRCUITS DIVISION

CPC5601

R04

www.ixysic.com

3.2 Programming Protocol

Figure 5. Latch Circuit Timing to Turn an Output On

A setup pulse on the input of at least 50

S starts the

bit programming sequence. The trailing edge of the

setup pulse starts a timer on the CPC5601 (t0). After

140

S, the value of the input is latched into the shift

To set an output, hold the input high for 200

S from

the leading edge after the setup pulse. This turns on

the corresponding open-drain FET to sink current.

Figure 6. Latch Circuit Timing to Turn an Output Off

To clear an output, hold the input high for 50

S after

the setup pulse, then take the input low for at least 150

S.

Repeat the sequence of the setup pulse followed by

the appropriate input condition for each successive bit.

Bear the following in mind while programming the

CPC5601:

• All bits must be set in each programming sequence,

even to change just one of the outputs.

• Data is placed in least-significant bit (output 1) first.

• After setting all the bits, take the input low. In the

absence of low-to-high transitions on the input, the

internal CPC5601 clock is held high, preventing any

output changes.

• The CPC5601 does not employ a shift register load

function. As new data is shifted into the flip-flops, the

outputs (starting with b1) change throughout the

data input sequence.

3.3 Programming Example

This programming example sets the following

CPC5601 output state, suitable for a European DAA:

INPUT (pin 3)

CLOCK

B1 (pin 13)

140 s



200 s



B1 output FET on (sinking current)

B1 output FET (drain open)

>=50 s (tsetup)



thold

Transition after setup time

initiates clock pulse

First

reads data

at the rising edge of the clock

B1 output FET (drain open)

Transition after setup time

initiates clock pulse

First

reads data

at the rising edge of the clock

INPUT (pin 3)

CLOCK

B1 (pin 13)

140 s

B1 output FET on (sinking current)

50 s

>=50 s (tsetup)

150 s min

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