DP83916 datasheet(60/96 Pages) NSC

No. de pieza	DP83916

Descripción Electrónicos	SONICTM-16 Systems-Oriented Network Interface Controller

PDF	96 Pages

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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60 / 96 page

50 Bus Interface (Continued)

5454 Memory Cycle for BMODE e 0 Synchronous

Mode

On the rising edge of T1 the SONIC-16 asserts ADS and

ECS to indicate that the memory cycle is starting The ad-

dress (A23 – A1) bus status (S2 – S0) and the direction

strobe (MWR) are driven and do not change for the remain-

der of the memory cycle On the falling edge of T1 the

SONIC-16 deasserts ECS ADS is deasserted on the rising

edge of T2

In Synchronous mode RDYi is sampled on the rising edge

at the end of T2 (the rising edge of the next T1 or Tx) T2

states will be repeated until RDYi is sampled properly in a

low state RDYi must meet the setup and hold times with

respect to the rising edge of bus clock for proper operation

During read cycles (

Figures 5-14 ) data (D15 – D0) is latched

at the rising edge at the end of T2 For write cycles (

Figure

5-15 ) data is driven on the falling edge of T1 and stays

driven until the end of the cycle

TLF11722 – 38

FIGURE 5-14 Memory Read BMODEe0 Synchronous (1 Wait-State)

TLF11722 – 40

FIGURE 5-15 Memory Write BMODEe0 Synchronous (1 Wait-State)

DP83916 Datasheet(PDF) 60 Page - National Semiconductor (TI)