V62SLASH12615-01XE-R datasheet(6/92 Pages) TI1

6 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

www.ti.com

List of Tables

2-1

Serial Management Interface

................................................................................................... 12

2-2

MAC Data Interface

.............................................................................................................. 12

2-3

Clock Interface

.................................................................................................................... 13

2-4

LED Interface

..................................................................................................................... 14

2-5

JTAG Interface

.................................................................................................................... 14

2-6

Reset and Power Down

......................................................................................................... 14

2-7

Strap Options

..................................................................................................................... 15

2-8

10 Mb/s and 100 Mb/s PMD Interface

......................................................................................... 16

2-9

Special Connections

............................................................................................................. 16

2-10

Power Supply Pins

............................................................................................................... 16

4-1

Auto-Negotiation Modes

......................................................................................................... 37

4-2

PHY Address Mapping

.......................................................................................................... 39

4-3

LED Mode Select

................................................................................................................. 41

5-1

Supported Packet Sizes at ±50ppm and ±100ppm for Each Clock

....................................................... 45

5-2

Typical MDIO Frame Format

................................................................................................... 47

6-1

4B5B Code-Group Encoding or Decoding

.................................................................................... 49

7-1

25 MHz Oscillator Specification

................................................................................................ 59

7-2

50 MHz Oscillator Specification

................................................................................................ 59

7-3

25 MHz Crystal Specification

................................................................................................... 60

9-1

...................................................................................................................... 64

9-2

.................................................................................................................... 65

9-3

Basic Mode Control Register (BMCR), Address 0x00

....................................................................... 68

9-4

Basic Mode Status Register (BMSR), Address 0x01

........................................................................ 69

9-5

PHY Identifier Register #1 (PHYIDR1), Address 0x02

...................................................................... 70

9-6

PHY Identifier Register #2 (PHYIDR2), Address 0x03

...................................................................... 70

9-7

Negotiation Advertisement Register (ANAR), Address 0x04

............................................................... 71

9-8

Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), Address 0x05

............................... 72

9-9

Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), Address 0x05

................................. 72

9-10

Auto-Negotiate Expansion Register (ANER), Address 0x06

............................................................... 73

9-11

Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x07

.............................................. 74

9-12

PHY Status Register (PHYSTS), Address 0x10

............................................................................. 74

9-13

MII Interrupt Control Register (MICR), Address 0x11

....................................................................... 76

9-14

MII Interrupt Status and Miscellaneous Control Register (MISR), Address 0x12

........................................ 77

9-15

False Carrier Sense Counter Register (FCSCR), Address 0x14

.......................................................... 78

9-16

Receiver Error Counter Register (RECR), Address 0x15

................................................................... 78

9-17

100 Mb/s PCS Configuration and Status Register (PCSR), Address 0x16

............................................... 78

9-18

RMII and Bypass Register (RBR), Addresses 0x17

......................................................................... 79

9-19

LED Direct Control Register (LEDCR), Address 0x18

...................................................................... 80

9-20

PHY Control Register (PHYCR), Address 0x19

.............................................................................. 80

9-21

10Base-T Status/Control Register (10BTSCR), Address 0x1A

............................................................ 82

9-22

CD Test and BIST Extensions Register (CDCTRL1), Address 0x1B

..................................................... 83

9-23

Energy Detect Control (EDCR), Address 0x1D

.............................................................................. 83

List of Tables

V62/12615-01XE-R Datasheet(PDF) 6 Page - Texas Instruments

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