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DP83256VF Datasheet(PDF) 76 Page - National Semiconductor (TI) |
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DP83256VF Datasheet(HTML) 76 Page - National Semiconductor (TI) |
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76 / 144 page  50 Registers (Continued) 532 CMT CONDITION COMPARISON REGISTER (CMTCCR) The CMT Condition Comparison Register (CMTCR) ensures that the Control Bus must first read a bit modified by the PLAYERa device before it can be written to by the Control Bus Interface The current state of the CMT Condition Register (CMTCR) is automatically written into the CMT Condition Comparison Register (CMTCR) (ie CMTCCR e CMTCR) during a Control Bus Interface read-cycle of CMTCR During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt Control Register (ICR) to 1 and disallow the setting or clearing of a bit within the CMTCR when the value of a bit in the CMTCR differs from the value of the corresponding bit in the CMT Condition Comparison Register ACCESS RULES ADDRESS READ WRITE 1Fh Always Always D7 D6 D5 D4 D3 D2 D1 D0 TCOC STEC RES RES RES RES RES RES Bit Symbol Description D0-D5 RES RESERVED Reserved for future use D6 STEC SCRUB TIMER EXPIRED COMPARISON The comparison bit for the Scrub Timer Expire bit (STE) of the CMT Condition Register (CMTCR) D7 TCOC TRIGGER CONDITION OCCURRED COMPARISON The comparison bit for the Trigger Condition Occurred (TCO) bit of the CMT Condition Register (CMTCR) 76 |
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