8

®

AFE1203

TIMING DIAGRAM

FIGURE 3. Timing Diagram.

RECEIVE TIMING

The rxSYNC signal controls portions of the A/D converter’s

decimation filter and the data output timing of the A/D

converter. It is generated at the symbol rate by the user and

must be synchronized with txCLK. The leading edge of

rxSYNC can occur at the leading edge of txCLK or it can be

shifted by the user in increments of 1/16 of a symbol period

to one of 15 discrete delay times after the leading edge of

txCLK.

RECEIVE OUTPUT DATA RATE

The receive channel delta-sigma A/D converter of the

AFE1203 uses a modulator which operates at an oversampling

rate of 24X the symbol rate. The A/D converter’s decimation

filter downsamples the modulator output by a factor of 12.

The bandwidth of the decimation filter is equal to one-half

the symbol rate. This yields two output words per symbol

period. These two output words are shown as Data 1 and

Data 1a in Figure 3. The specifications of the AFE1203

assume that one A/D converter output is used per symbol

period and the other output is ignored. The Receive Timing

diagram above suggests using the rising edge of the rxSYNC

pulse to read the first data output in a symbol period. Either

data output may be used. Both data outputs may be used for

more flexible post-processing.

t

tx1

t

tx2

t

t

nt

nt

Data 1

Data 1a

Data 2

3t

txCLK

Transmit Timing

txDAT

txDAT

txDAT

txDAT

rxSYNC

Receive Timing

rxD13 - rxD0

t

nt

5ns

5ns

NOTES: (1) Any transmit sequence not shown will result in a zero symbol. (2) All transitions are specified relative to the rising edge of

txCLK. (3) Maximum allowable error for any txDAT edge is

±t

(5) Both txDAT inputs are read by the AFE12 03 at 1/8, 3/8, and 5/8 of a symbol period from the rising edge of txCLK. (6) rxSYNC can

shift to one of 16 discrete delay times from the rising edge of txCLK. (7) It is recommended that rxD13 - rxD0 be read on the rising edge

of rxSYNC.

5ns

5ns