DP83256 datasheet(23/144 Pages) NSC

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30 Functional Description (Continued)

35 CLOCK GENERATION MODULE

The Clock Generation Module is an integrated phase locked

loop that generates all of the required clock signals for the

PLAYERa device and the rest of an FDDI system from a

single 125 MHz reference

The Clock Generation Module features

High precision clock timing generated from a single

125 MHz reference

Multiple precision phased (8 ns16 ns) 125 MHz Local

Byte Clocks to eliminate timing skew in large multi-board

concentrator configurations

LBC timing which is insensitive to loading variations over

a wide range (20 pF to 70 pF) of LBC loads

A selectable dual frequency system clock

Low clock edge jitter due to high VCO stability

The Clock Generation Module is comprised of 6 main func-

tional blocks

Reference Selector

Phase Comparator

Loop Filter

250 MHz Voltage Controlled Oscillator

Output Phasing and Divide by 10

See

Figure 3-18 Clock Generation Module Block Diagram

REFERENCE SELECTOR

The Reference Selector block allows the user to choose

between 2 sources for the Clock Generation Module’s

125 MHz reference clock

The simplest reference clock source option is to use an

external 125 MHz reference signal fed into the REF

input This input can come from a crystal oscillator module

or from a Local Byte Clock generated by another PLAYERa

device Using the appropriate crystal oscillator ensures cor-

rect operating frequency without having to adjust any dis-

crete components

Using an LBC clock from another PLAYERa device allows

one PLAYERa device to create a master clock to which

other PLAYERa devices in a system can be synchronized

Another reference clock source option is a local 125 MHz

crystal circuit An example crystal circuit with component

values is shown in

Figure 3-19 This circuit is designed to

operate with a crystal that has a CL of 15 pF The capacitor

values may need to be slightly adjusted for an individual

application to accomodate differences in parasitic loading

The REF

SEL signal selects between the two references

Component Values

Crystal 1250000 MHz

270X 5%

CISO

56 pF (1%)

CIN

54 pF (1%)

COUT

54 pF (1%)

TLF11708 – 22

FIGURE 3-19 Crystal Circuit

PHASE COMPARATOR

The Phase Comparator uses two signal inputs the selected

125 MHz reference from the Reference Select Block and a

Local Byte Clock that has been selected for the feedback

input FBK

IN Typically LBC1 is used as the feedback

clock

The Phase Comparator generates a pulse of current that is

proportional to the phase difference between the two sig-

nals The current pulses are used to charge and discharge a

control voltage on the internal Loop Filter This control volt-

age is used to minimize the phase difference between the

two signals

LOOP FILTER

The Loop Filter is a simple internal filter made up of one

capacitor in parallel with a serial capacitor and resistor com-

bination One end of the filter is connected to Ground and

the other node is driven by the Phase Comparator and con-

trols the internal 250 MHz Voltage Controlled Oscillator

This node can be examined for diagnostic purposes on the

LPFLTR pin when the FLTREN bit of the CGMREG register

is enabled The LPFLTR pin is provided for diagnostic pur-

poses only and should not be connected in any application

TLF11708 – 21

FIGURE 3-18 Clock Generation Module Block Diagram

DP83256 Datasheet(PDF) 23 Page - National Semiconductor (TI)

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