| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADS5541IPAPR Datasheet(PDF) 11 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADS5541IPAPR Datasheet(HTML) 11 Page - Texas Instruments |
|
11 / 37 page ![]() www.ti.com Production Data ADS5541 SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS(1) TERMINAL NO. OF NAME NO. PINS I/O DESCRIPTION AVDD 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 12 I Analog power supply 6, 8, 12–14, 16, 18, 21, 23, 25, 27, 32, AGND 14 I Analog ground (PowerPAD must be connected to analog ground). 36, 38 DRVDD 49, 58 2 I Output driver power supply DRGND 1, 42, 48, 50, 57, 59 6 I Output driver ground INP 19 1 I Differential analog input (positive) INM 20 1 I Differential analog input (negative) Reference voltage (positive); 1 µF capacitor in series with a 1Ω REFP 29 1 O resistor to GND. Reference voltage (negative); 1 µF capacitor in series with a 1Ω REFM 30 1 O resistor to GND. IREF 31 1 I Current set; 56k Ω resistor to GND; do not connect capacitors. CM 17 1 O Common-mode output voltage RESET 35 1 I Reset (active high); Internal 200k Ω resistor to AV DD. (2) OE 41 1 I Output enable (active high)(3) DFS 40 1 I Data format and clock out polarity select(4)(3) CLKP 10 1 I Data converter differential input clock (positive) CLKM 11 1 I Data converter differential input clock (negative) SEN 4 1 I Serial interface chip select(3) SDATA 3 1 I Serial interface data(3) SCLK 2 1 I Serial interface clock(3) D0 (LSB)–D13 (MSB) 44–47, 51–56, 60–63 12 O Parallel data output OVR 64 1 O Over-range indicator bit CLKOUT 43 1 O CMOS clock out in sync with data (1) PowerPAD is connected to analog ground. (2) If RESET pin is unused, it must be tied to AGND and serial interface should be used to reset the device. See the serial programming interface section for details. (3) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins must also run off the same supply voltage as DRVDD. (4) Table 3 defines the voltage levels for each mode selectable via the DFS pin. 11 Submit Documentation Feedback |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |