T/H

10-BIT

SUCCESSIVE

APPROXIMATION

ADC

SCLK

CS

SDATA

CONTROL

LOGIC

1

2

3

4

5

6

CS

GND

SDATA

SCLK

ADC101S021

ADC101S021

SNAS307G – JULY 2005 – REVISED JANUARY 2014

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. Key Specifications

VALUE

UNIT

DNL

+0.16 / -0.09

LSB (typ)

INL

+0.14 / -0.13

LSB (typ)

SNR

61.6

dB (typ)

Power Consumption

3.6V Supply

2.34

mW (typ)

5.25V Supply

8.9

mW (typ)

Resolution

Specified for Sample Rate Range of:

50 to 200 ksps

200 to 500 ksps

500 ksps to 1 Msps

12-bit

ADC121S021

ADC121S051

ADC121S101

10-bit

ADC101S021

ADC101S051

ADC101S101

8-bit

ADC081S021

ADC081S051

ADC081S101

(1)

All devices are fully pin and function compatible.

Connection Diagram

Figure 1. 6-Lead SOT-23 or WSON

See DBV or NGF Package

Block Diagram

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Description

ANALOG I/O

3

DIGITAL I/O

4

SCLK

Digital clock input. This clock directly controls the conversion and readout processes.

2

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