2

Pinout

CD54HC138, CD54HCT138, CD54HC238, CD54HCT238

(CERDIP)

CD74HC138, CD74HCT138, CD74HCT238

(PDIP, SOIC)

CD74HC238

(PDIP, SOIC, SOP, TSSOP)

TOP VIEW

Signal names in parentheses are for ’HC138 and ’HCT138.

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

A0

A1

A2

E1

E2

E3

GND

(Y7) Y7

Y1 (Y1)

Y2 (Y2)

Y3 (Y3)

Y4 (Y4)

Y5 (Y5)

Y6 (Y6)

Y0 (Y0)

15

14

13

12

10

7

9

11

1

2

3

5

6

4

E3

E2

E1

A2

A1

A0

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

HC/HCT

238

HC/HCT

138

TRUTH TABLE ’HC138, ’HCT138

INPUTS

OUTPUTS

ENABLE

ADDRESS

E3

E2

E1

A2

A1

A0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

X

H

X

X

X

HHHHHHHH

L

X

X

X

X

X

HHHHHHHH

X

H

X

X

X

X

HHHHHHHH

H

L

LLLLL

H

H

H

H

H

H

H

H

L

L

L

L

H

H

L

HHHHHH

H

L

L

L

H

L

HH

L

H

HHHH

H

L

L

L

HHHHH

L

HHHH

H

L

L

H

L

L

HHHH

L

HHH

H

L

L

H

L

HHHHHH

L

H

H

H

L

L

H

H

L

HHHHHH

L

H

H

L

L

H

HHHHHHHHH

L

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

TRUTH TABLE ’HC238, ’HCT238

INPUTS

OUTPUTS

ENABLE

ADDRESS

E3

E2

E1

A2

A1

A0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

X

H

X

X

X

LLLLLLLL

L

X

X

X

X

X

LLLLLLLL

X

H

X

X

X

X

LLLLLLLL

H

L

LLLL

H

LLLLLLL

H

L

LLL

H

L

H

LLLLLL

H

L

LL

H

L

LL

H

L

LLLL

H

L

LL

H

H

LLL

H

LLLL

H

L

L

H

LLLLLL

H

L

LL

HL

LHLHL

L

L

L

LHL

L

H

L

L

H

H

L

LLLLLL

H

L

H

L

L

H

H

H

LLLLLLL

H

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238