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HCF4021B Datasheet(PDF) 1 Page - STMicroelectronics |
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HCF4021B Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page  1/11 September 2001 s MEDIUM SPEED OPERATION : 12 MHz (Typ.) CLOCK RATE AT VDD - VSS = 10V s FULLY STATIC OPERATION s 8 MASTER-SLAVE FLIP-FLOPS PLUS OUTPUT BUFFERING AND CONTROL GATING s QUIESCENT CURRENT SPECIFIED UP TO 20V s 5V, 10V AND 15V PARAMETRIC RATINGS s INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C s 100% TESTED FOR QUIESCENT CURRENT s MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4021B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is an 8-stage parallel or serial input/ serial output register having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous. In this device, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of he clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple package is permitted. HCF4021B ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER PIN CONNECTION ORDER CODES PACKAGE TUBE T & R DIP HCF4021BEY SOP HCF4021BM1 HCF4021M013TR DIP SOP |
Número de pieza similar - HCF4021B |
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Descripción similar - HCF4021B |
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