CS5530 datasheet(230/241 Pages) NSC

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Revision 4.1

Electrical Specifications (Continued)

5.6

AC CHARACTERISTICS

The following tables list the AC characteristics including

output delays, input setup requirements, input hold

requirements and output float delays. The rising-clock-

edge reference level, VREF, and other reference levels are

shown in Table 5-7. Input or output signals must cross

these levels during testing.

Input setup and hold times are specified minimums that

define the smallest acceptable sampling window for which

a synchronous input signal must be stable for correct oper-

ation.

Note:

All AC tests are at VDD = 3.0V to 3.6V, TC =0

oCto

85oC, CL = 50 pF unless otherwise specified.

Figure 5-2. Drive Level and Measurement Points for Switching Characteristics

Table 5-7. Drive Level and Measurement Points

for Switching Characteristics

Symbol

Voltage (V)

VREF

1.5

VIHD

2.3

VILD

0.3

CLK

OUTPUTS

INPUTS

VIHD

VILD

VREF

Valid Input

Valid Output n+1

Valid Output n

VREF

VILD

VIHD

Min

Max

Legend: A = Maximum Output Delay Specification

B = Minimum Output Delay Specification

C = Minimum Input Setup Specification

D = Minimum Input Hold Specification

Table 5-8. AC Characteristics of Specification Compliant Interface Signals

Interface Signal Group

Specification Name

IDE Interface Signals

ATA-4 Specification

USB Interface Signals

USB Specification, Version 1.0

PCI Bus Interface Signals

PCI Bus Specification, Revision 2.1

ISA Bus Interface Signals

Abides industry standards

Note:

The interface signal groups listed in Table 5-8 adhere to the timing parameters given in the corresponding

specification. For details, refer to those specifications.

CS5530 Datasheet(PDF) 230 Page - National Semiconductor (TI)

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