CS5530 datasheet(96/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

Since the two controllers are cascaded and three of the

interrupt request inputs are connected to the internal 8254

PIT, the coprocessor interface, and the real-time clock

interface, a total of 13 external interrupt requests are

available. See Table 3-42.

The CS5530 allows the PCI interrupt signals INTA#-

INTD#(also knowninindustryterms as PIRQx#) tobe

routed internally to any IRQ signal. The routing can be

modified through CS5530’s configuration registers. If this

is done, the IRQ input must be configured to be level-

rather than edge-sensitive. IRQ inputs may be individually

programmed to be active low, level-sensitive with the

Interrupt Sensitivity configuration registers at I/O address

space 4D0h and 4D1h. PCI interrupt configuration is dis-

cussed in further detail in Section 3.5.4.4 “PCI Compatible

Interrupts” on page 98.

PIC Interrupt Sequence

A typical AT-compatible interrupt sequence is as follows.

Any unmasked interrupt generates the INTR signal to the

CPU. The interrupt controller then responds to the inter-

rupt acknowledge (INTA) cycles from the CPU. On the first

INTA cycle the cascading priority is resolved to determine

which of the two 8259 controllers output the interrupt vec-

tor onto the data bus. On the second INTA cycle the

appropriate 8259 controller drives the data bus with the

correct interrupt vector for the highest priority interrupt.

By default, the CS5530 responds to PCI INTA cycles

because the system interrupt controller is located within

the CS5530. This may be disabled with F0 Index 40h[7]

(see Table 3-43). When the CS5530 responds to a PCI

INTA cycle, it holds the PCI bus and internally generate

the two INTA cycles to obtain the correct interrupt vector.

It then asserts TRDY# and returns the interrupt vector.

PIC I/O Registers

Each PIC contains registers located in the standard I/O

address locations, as shown in Table 4-28 "Programmable

Interrupt Controller Registers" on page 213.

An initialization sequence must be followed to program

the interrupt controllers. The sequence is started by writ-

ing Initialization Command Word 1 (ICW1). After ICW1

has been written, the controller expects the next writes to

follow in the sequence ICW2, ICW3, and ICW4 if it is

needed. The Operation Control Words (OCW) can be

written after initialization. The PIC must be programmed

before operation begins.

Since the controllers are operating in cascade mode,

ICW3 of the master controller should be programmed with

a value indicating that IRQ2 input of the master interrupt

controller is connected to the slave interrupt controller

rather than an I/O device as part of the system initializa-

tion code. In addition, ICW3 of the slave interrupt control-

ler should be programmed with the value 02h (slave ID)

and corresponds to the input on the master controller.

Table 3-42. PIC Interrupt Mapping

Master IRQ#

Mapping

IRQ0

Connected to the OUT0 (system timer) of

the internal 8254 PIT.

IRQ2

Connected to the slave’s INTR for a cas-

caded configuration.

IRQ8#

Connected to external real-time clock.

IRQ13

Connected to the coprocessor interface.

IRQ[15:14, 12:9,

7:3, 1]

External interrupts.

Table 3-43. PCI INTA Cycle Disable/Enable Bit

Bit

Description

F0 Index 40h

PCI Function Control Register 1 (R/W)

Reset Value = 89h

PCI Interrupt Acknowledge Cycle Response: The CS5530 responds to PCI interrupt acknowledge cycles:

0 = Disable; 1 = Enable.

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