MPC875 datasheet(68/84 Pages) FREESCALE

68 / 84 page

MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

FEC Electrical Characteristics

Table 31 provides information on the MII receive signal timing.

Figure 64 shows MII receive signal timing.

Figure 64. MII Receive Signal Timing Diagram

15.2 MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK

frequency – 1%.

Table 32 provides information on the MII transmit signal timing.

Table 31. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup

—

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

—

MII_RX_CLK pulse width high

35%

65%

MII_RX_CLK period

MII_RX_CLK pulse width low

35%

65%

MII_RX_CLK period

M1_R

MII

RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK

setup

4—

M2_R

MII

RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR

hold

2—

Table 32. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

—

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

—

MII_TX_CLK pulse width high

35%

65%

MII_TX_CLK period

MII_TX_CLK pulse width low

35%

65%

MII_TX_CLK period

MII_RX_CLK (input)

MII_RXD[3:0] (inputs)

MII_RX_DV

MII_RX_ER

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