MSK5061RH datasheet(4/11 Pages) MSK

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APPLICATION NOTES

PIN FUNCTIONS

VIN – The VIN pins are the input supply pins for all of

the internal circuitry. High di/dt switching currents are

conducted through these pins. Locally decouple VIN to

PGND with a mix high frequency ceramic capacitors and

low ESR tantalum. Provide sufficient bulk capacitance

to ensure a low impedance buss and limit input voltage

ripple.

PGND – The PGND pins connect to the internal power

ground plane. High di/dt switching currents are conduct-

ed through these pins. Provide a continuous low imped-

ance ground path between the MSK5061RH PGND, the

input supply return, and the load. Avoid layouts that force

load return current to cross the AGND reference path.

VOUT – The VOUT pins are connected to the internal

output inductor. Connect VOUT as close as possible to

the load to minimize bus impedance. Connecting 500 to

1000µF low ESR bulk capacitance to VOUT is typical-

ly sufficient to ensure stable operation. Some ceramic

capacitance near the load is typically required to roll off

high frequency gain, suppress switching noise and fast

load transients. A mix of high frequency ceramic capaci-

tors and low ESR tantalum are recommended. See Out-

put Capacitor Selection paragraph.

AGND – The AGND pin provides a low noise signal ref-

erence for the internal control circuitry. For optimum reg-

ulation performance, connect AGND and PGND together

near the ground side of the load.

PGND1/CASE – This pin is electrically connected to the

MSK5061RH case and PGND.

FB – The FB pin is the inverting input to the error ampli-

fier. The voltage at this pin and the 0.6V reference volt-

age are used to servo to current control loop set point.

Place a resistor divider between VOUT and AGND near

the load, and connect the FB pin to the center node to

program the output voltage. See Output Voltage Selec-

tion paragraph.

REF – The REF pin is the internal 0.6V reference voltage

used in several circuit functions. The reference voltage is

pined out for current sharing applications. When apply-

ing the 2 phase current sharing functionality, connect the

REF pins of the master and slave MSK5061RHs through

a 10Ω resistor. This pin must not be otherwise loaded.

FSEL – The FSEL pin is used to program the Switching

frequency of the MSK5061RH. Connect to VIN for 1MHz

or to PGND for 500KHz operation.

PORSEL – The PORSEL pin is used to program the power

on reset thresholds of the MSK5061RH. Connect to VIN

for a 5V nominal input bus, or PGND for a 3.3V nominal

input bus. Connect to PGND for a input bus that varies

from 3V to 5.5V.

SS – The Soft Start pin provides control of turn on surge

currents and enables coincident or ratiometric tracking

functionality. A 23µA current source charges the internal

SS capacitor and sets the output ramp rate to approxi-

mately 2.6mS. Connect additional capacitance to reduce

the output ramp rate. In 2 phase current sharing applica-

tions, the slave ramp rate should be at least twice that of

the master. Further application guidance is provided in the

Start Up Considerations section.

EN – The EN pin provides hysteretic on/off control of the

regulator. Driving this pin above 0.6V enables the regula-

tor. Programmable hysteresis is realized with an 11µA cur-

rent sink that is active until the pin voltage exceeds VREF.

Bypass with a capacitor to ground when controlling from a

high impendence source. See the applications section for

further guidance.

PGOOD – The PGOOD pin is a high impedance logic out-

put that is pulled low when the regulators output voltage is

outside of a ±11% typical window. This status flag can be

used for supply sequencing and fault detection.

M/S – The M/S input pin determines the function of the

bidirectional SYNC pin. Connect M/S to VIN for Master

mode, where the SYNC pin is the master oscillator output.

Connect M/S to PGND for Slave mode, where SYNC be-

comes an input.

SYNC – When SYNC is configured as an output, M/S = VIN,

this pin drives the SYNC pin input of another MSK5061RH

with a square wave that is phase shifted ≈180° from the

Master clock driving the Master PWM circuits. When con-

figured as an input, M/S = PGND, this pin uses the SYNC

output from another MSK5061RH or an external clock to

clock the PWM circuitry. If synchronizing to an external

clock, the clock must be SEE hardened and the frequency

must be within the range of 400kHz to 1.2MHz.

PRELIMINARY Rev. B 3/15

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