COP688CL datasheet(15/40 Pages) NSC

15 / 40 page

Timers (Continued)

TLDD9766 – 11

FIGURE 6 Timers

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode This IDLE

mode support is furnished by the IDLE timer T0 which is a

16-bit timer The Timer T0 runs continuously at the fixed

rate of the instruction cycle clock tc The user cannot read

or write to the IDLE Timer T0 which is a count down timer

The Timer T0 supports the following functions

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

The IDLE Timer T0 can generate an interrupt when the thir-

teenth bit toggles This toggle is latched into the T0PND

pending flag and will occur every 4 ms at the maximum

clock frequency (tc e 1 ms) A control flag T0EN allows the

interrupt from the thirteenth bit of Timer T0 to be enabled or

disabled Setting T0EN will enable the interrupt while reset-

ting it will disable the interrupt

TIMER T1 AND TIMER T2

The device has a set of two powerful timercounter blocks

T1 and T2 The associated features and functioning of a

timer block are described by referring to the timer block Tx

Since the two timer blocks T1 and T2 are identical all com-

ments are equally applicable to either timer block

Each timer block consists of a 16-bit timer Tx and two

supporting 16-bit autoreloadcapture registers RxA and

RxB Each timer block has two pins associated with it TxA

and TxB The pin TxA supports IO required by the timer

block while the pin TxB is an input to the timer block The

powerful and flexible timer block allows the device to easily

perform all timer functions with minimal software overhead

The timer block has three operating modes Processor Inde-

pendent PWM mode External Event Counter mode and

Input Capture mode

The control bits TxC3 TxC2 and TxC1 allow selection of

the different modes of operation

Mode 1 Processor Independent PWM Mode

As the name suggests this mode allows the device to gen-

erate a PWM signal with very minimal user intervention

The user only has to define the parameters of the PWM

signal (ON time and OFF time) Once begun the timer block

will continuously generate the PWM signal completely inde-

pendent of the microcontroller The user software services

the timer block only when the PWM parameters require up-

dating

In this mode the timer Tx counts down at a fixed rate of tc

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers RxA and RxB The very

first underflow of the timer causes the timer to reload from

the register RxA Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The Tx Timer control bits TxC3 TxC2 and TxC1 set up the

timer for PWM mode operation

Figure 7 shows a block diagram of the timer in PWM mode

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COP688CL Datasheet(PDF) 15 Page - National Semiconductor (TI)

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