CLC949 datasheet(7/12 Pages) NSC

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with a frequency of 1/2 the sample rate. The bias current

was then turned up until the SNR was better than 65dB

and the SFDR exceeded 72dB.

The axis on the left

shows the power that was dissipated by the device as a

function of speed, whereas the other curve uses the axis

on the right to show the resistor value required to obtain

this bias.

Figure 6: Power Dissipation & Programming

Resistor vs. Sample Rate

Dynamic Power Down

In systems where you do not use the A/D converter con-

tinually, and low power consumption is a key require-

ment, the power to the CLC949 can be turned down while

it is not being used. This is done through the use of the

BIASC pin, and a programming resistor to the power

supply. When the potential on this resistor is brought low,

the part goes into a sleep mode which saves power. This

can be accomplished by connecting the bias setting

resistor to a CMOS gate as shown in Figure 7. In sleep

mode the CLC949 will draw approximately 8mA, or

40mW on a 5V supply.

Figure 7: Dynamic Power Savings

PCB Layout

The

keys

successful

CLC949

layout

are

a substantial low-impedance ground plane, short

connections in and out of the data converter, and proper

power supply decoupling. The use of a socket for the

final design is not recommended but if one must be used

during debug or prototyping, then Comlinear recommends

the McKenzie #PLCC-44P-T-SMT socket which has low

parasitic impedances. The traces from the clock source

to the CLC949 should be as short as possible, if forced

to put the clock driver more than a couple of

centimeters away from the CLC949, then add a buffer for

the clock right next to the CLC949.

There is an evaluation board available for the CLC949

(E949PCASM)

This board can be used to quickly

evaluate the performance of the CLC949 data converter.

Use of this evaluation board as a model for your PCB lay-

out is recommended.

The schematic for this evaluation

board is shown in Figure 8 on the following page. The

board layout for the E949PCASM is shown in the

E949PCASM datasheet.

Power Supplies, Grounding and Bypassing

To obtain the best possible performance from high speed

devices, you must pay close attention to power supplies,

bypassing and grounding. This applies not only to the

A/D converter itself but to the entire system.

The recommended supply decoupling scheme for the

CLC949 includes:

• One 0.01 to 0.033µF capacitor between each

power pin and GND.

• One 6.8 to 10µF capacitor per board, placed no

more than a few inches from the A/D connected

between VDD and GND.

• One 0.1µF capacitor from each of the reference

inputs (VREFP, VREFN, VREFPC, VREFNC) to GND.

• If the board has supplies that include excessive

digital switching noise, then ferrite beads in series

with the power feed to the A/D should also be

included.

• Proper bypassing of all other integrated circuits

on the board, especially digital logic I.C.s.

CLC949

CMOS Inverter

VDD

BC0

BIASC

BC1

Sleep

10k

*See Figure 6 above.

Rp*

Power Dissipation & Programming

Resistor vs. Sample Rate

Sample Rate (MSPS)

200

150

100

Power

Resistor

Ordering Information

Model

Temperature Range

Description

CLC949ACQ

0˚C to +70˚C

44-pin PLCC

CLC949AJQ

-40˚C to +85˚C

44-pin PLCC

Package Thermal Resistance

Package

44-pin PLCC

°C/W

Power Requirements

Typ

Units

Vcc = +5V, 5MSPS, Low Bias

Vcc = +5V, 20MSPS, Med Bias

220

Vcc = +5V, 30MSPS, High Bias

400

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