CLC935BC datasheet(8/12 Pages) NSC

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analog input range =

± [2V + (0.129)(VGAIN ADJUST - 2.5V)]

GAIN ADJUST pin(33)

Analog Input Range

Voltage

1.0V

1.8Vpp

2.5V or open

2.0Vpp

4.0V

2.2Vpp

Analog Input Range Adjust Circuit

A resistor from GAIN ADJUST to ground provides a

second method of adjusting the analog input range. This

technique will decrease the data converter’s gain and

increase the analog input range.

Alternate Input Range Adjust Circuit

Offset Adjust

Typically the center of the ±1V analog input range is laser

trimmed to 0V during construction. By applying a voltage

at the OFFSET ADJUST (pin 36), the analog input offset

can be adjusted approximately ±100mV around ground.

The applied voltage at pin 36 can range from GROUND

to VOFFSET REFERENCE. If the OFFSET REFERENCE

(pin 37) voltage is used to generate the applied OFFSET

ADJUST voltage, adjustments in the analog input

range offset

will track any adjustments made to the

analog input range gain. Analog input range gain and

offset adjustments are tightly coupled when the OFFSET

REFERENCE is used to generate the OFFSET ADJUST

applied voltage. Self-calibration techniques for adjusting

offset and gain should use OFFSET REFERENCE in

adjusting the offset.

Analog input offset and gain adjustments can be made

independent of each other if the VREF OUT (pin 35) is

used to generate the applied OFFSET ADJUST voltage

instead of the OFFSET REFERENCE voltage.

If the

VREF OUT approach is adopted, the CLC935 offset and

gain will be independent of each other, but will likely need

an iterative adjustment approach where both offset and

gain are successively adjusted until the desired result is

obtained.

Offset Adjust Range

Analog Input Offset

pin (36)

VOFFSET REFERENCE

+100mV

open

0mV

GROUND

-100mV

Offset Adjust Circuit

The OFFSET ADJUST and GAIN ADJUST pins are

sensitive to noise; and should be bypassed to ground

with 0.1

µF ceramic capacitors. If the OFFSET ADJUST

and GAIN ADJUST pins are not used, then they should

be left floating.

CONVERT Clock Generation

All high-speed high-resolution A/D converters are sensi-

tive to the CONVERT clock quality.

With a full scale

7MHz analog input signal, the slew rate at the 0V cross-

ing is 90LSB/ns. An error (jitter) of as little as 5ps in the

clock edge will yield a 0.5LSB error at the A/D output.

This is as great or greater than any other error source

likely to be present. This type of clock error or clock jitter

is most easily seen in the form of poor SNR (signal-to-

noise ratio). If the SNR is below expectations, clock jitter

should be investigated.

It should also be noted that jitter in the analog input

source will have the same detrimental effect on SNR.

Analog input signal jitter is usually only a problem

evaluation setups, and

does not generally present a

problem in full systems.

Low-jitter crystal controlled oscillators make the best

CONVERT clock sources.

If the CONVERT clock is

generated from another type of source, by gating,

dividing or other method, it should be registered by the

original clock as the last step. This should keep jitter

terms from compounding.

2.500V

Ω

GAIN

ADJUST

0.500V

250

Ω

680

Ω

2.7k

Ω

OP14

100

Ω

0.1

µF

GAIN ADJUST

RANGE

1.0V

4.0V

CLC935

VREFOUT

GAIN

ADJUST

CLC935

R =

774 - 4,800

∆

Where

∆ is the gain change factor,

i.e 0.01 equals 1% change.

Voffset

REF, pin (37) is

nominally +3.1 V and

ranges from +3.4V to

+2.8V depending on

the specific GAIN

ADJUST voltage

at pin 33.

OFFSET

ADJUST

OP14

100

0.1

CLC935

OFFSET

REFERENCE

1.5K

Offset Adjust Range

Voffset

REF, to

(Voffset

REF, – 1.8V);

… Nominally

1.3V to 3.1V.

SNR

20log

2 f jitter

where :

jitter

clock jitter

analog jitter

MAX

RMS

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