Features

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0.0025% settling in 25ns (32ns max)

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0.5mV input offset voltage, 3

µV/°C drift

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±1 to ±8 closed-loop gain range

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Low power, 150mW

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0.01%/0.05° differential gain/phase

Applications

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High-accuracy A/D systems (12-14 bits)

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High-accuracy D/A converters

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High-speed communications

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IF processors

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Video distribution

General Description

CLC402

Low-Gain Op Amp with Fast 14-Bit Settling

N

June 1999

Pinout

DIP & SOIC

The CLC402 is available in several versions to meet a variety of

requirements. A three-letter suffix determines the version:

CLC402AJP -40°C to +85°C

8-pin plastic DIP

CLC402AJE -40°C to +85°C

8-pin plastic SOIC

CLC402A8B -55°C to +125°C

8-pin hermetic CERDIP,

MIL-STD-833, Level B

dice

CLC402AMC -55°C to +125°C

dice qualified to Method 5008,

MIL-STD-883, Level B

DESC SMD number: 5962-92033

© 1998 National Semiconductor Corporation

http://www.national.com

Printed in the U.S.A.

Non-Inverting Frequency Response

1

10

100

-180

-450

-270

-360

-90

0