SP6122 datasheet(13/19 Pages) SIPEX

13 / 19 page

Rev. 7/16/03

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

INPUT CAPACITOR SELECTION

The input capacitor should be selected for

ripple current rating, capacitance and volt-

age rating. The input capacitor must meet

the ripple current requirement imposed by

the switching current. In continuous con-

duction mode, the source current of the

high-side MOSFET is approximately a

square wave of duty cycle VOUT/VIN. Most of

this current is supplied by the input bypass

capacitors. The RMS value of input capaci-

tor current is determined at the maximum

output current and under the assumption

that the peak to peak inductor ripple current

is low, it is given by:

ICIN(RMS) = IOUT(MAX)√ D(1-D)

The worse case occurs when the duty cycle

D is 50% and gives an RMS current value

equal to IOUT/2. Select input capacitors with

adequate ripple current rating to ensure

reliable operation. The power dissipated in

the input capacitor is:

PCIN = ICIN2 (RMS) RESR(CIN)

This can become a significant part of power

losses in a converter and hurt the overall

energy transfer efficiency. The input volt-

age ripple primarily depends on

the input capacitor ESR and capacitance.

Ignoring the inductor ripple current, the in-

put voltage ripple can be determined by:

∆VIN = IOUT (MAX) RESR(CIN) +

IOUT(MAX)VOUT(VIN - VOUT)/( FS CIN VIN2)

The capacitor type suitable for the output

capacitors can also be used for the input

capacitors. However, exercise extra cau-

tion when tantalum capacitors are consid-

ered. Tantalum capacitors are known for

catastrophic failure when exposed to surge

current, and input capacitors are prone to

such surge current when power supplies

are connected ‘live’ to low impedance power

sources. Certain tantalum capacitors, such

as AVX TPS series, are surge tested. For

generic tantalum capacitors, use 2:1 volt-

age derating to protect the input capacitors

from surge fall-out.

For accurate control it is important to keep

ripple voltages on Vin to a minimum. Vin

powers the SP6122 and its internal refer-

ence used to maintain output regulation, so

proper input bypassing is critical to reduce

reference noise. With a reference compara-

tor internal hysteresis of 5mV, and a 1.25V

reference voltage, noise on the VCC of the

ICC should be kept to about 20mV or less to

reduce reference noise effect on output

regulation.

The use of very low ESR capacitors is recom-

mended for Vin bypassing, through the use of

parallel combinations of tantalum capacitors

or even better using some of the new large

valued multi-layer ceramic capacitors. ESR

values as low as 0.005Ω can be obtained with

a 47µF ceramic (see table 1 capacitor selec-

tion) and these ceramic capacitors will reduce

the power loss in the input capacitance greatly

by their reduced ESR values.

For the SP6122 example using the 47µF

ceramic input capacitor, the PCIN = 20mW,

which is very efficient, and the input ripple

voltage at the VIN post (not the VCC pin of the

IC) is about 90mV.

MOSFET SELECTION

A SP6122 design uses a PMOS switch on

the high side, without the need for a high

side charge pump, simplifying the applica-

tion circuit. The losses associated with the

PMOS can be divided into conduction and

switching losses. Conduction losses are

related to the on resistance of the PMOS,

and increase with the load current. Switch-

ing losses occur on each on/off transition

when the PMOS experiences both high

current and voltage. The switching losses

are difficult to quantify due to all the vari-

ables affecting turnon/turnoff time. How-

ever, the following equation provides an

approximation on the switching losses as-

sociated with the PMOS driven by SP6122.

APPLICATION INFORMATION: Continued

SP6122 Datasheet(PDF) 13 Page - Sipex Corporation

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