SC2597

5

Block Diagram

DRIV E R

L OGIC

VIN

7

VTT

8

GND

1

VD D

6

UV L O

S o ft-S ta rt

EN

2

VTTS

3

V DDQ

5

+

-

VR EF

4

EN \

R

R

T herm a l

S hutdow n

Pin #

Pin Name

Pin Function

1, PAD

GND

Ground reference for the IC.

2EN

Logic input to enable or disable the VTT output. If EN pin is grounded to shut down the linear regulator,

VREF remains active.

3

VTTS

VTT output sense input. Connect VTTS to the output at the output capacitor to implement remote sense.

4

VREF

The reference output, equal to one half of VDDQ. Connect a 100nF capacitor from this pin to GND.

5

VDDQ

External reference input; range 1V to 3.6V.

6

VDD

Input bias voltage — 2.35V to 3.6V . Connect a ceramic capacitor from this pin to GND.

7

VIN

LDO input range — 1V to 3.6V. Connect ceramic capacitors from this pin to GND.

8

VTT

Output of the linear regulator. Connect ceramic capacitors from this pin to GND.

Pin Descriptions