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VS6955CA Datasheet(PDF) 20 Page - STMicroelectronics |
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VS6955CA Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 90 page ![]() Functional description VS6955CA 20/90 DocID028071 Rev 2 3.5 External clock 3.5.1 PLL and clock input The VS6955CA has an embedded PLL block. This block generates all necessary internal clocks from an input range defined in Table 7. The value of the external clock frequency must be written to the register 0x0136 (extclk_frequency_mhz). 3.5.2 Clock input type The external clock provided by the host to the VS6955CA must be a DC coupled square wave and may also be RC-filtered. Figure 9. Clock input types Table 6. POR cell characteristics Symbol Constraint Minimum Typical Maximum Units VTRIGR POR rise voltage detection 0.95 V VTRIGF POR fall voltage detection 0.4 V Tburst (pw) Burst filter 2 8 µs Tpor Delay duration 20 45 µs Table 7. System input clock frequency range Minimum (MHz) Maximum (MHz) 6 27 Pad Pad Extclk extclk Camera module Host processor Pad Pad Extclk extclk Camera module Host processor 1st option DC-coupled 2nd option DC-coupled and filtered pwrdn pwrdn pwrdn pwrdn |
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