PEB20534 datasheet(21/439 Pages) INFINEON

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PEB 20534

PEF 20534

Overview

Data Sheet

2000-05-30

– Programmable Preamble (8 bit) with selectable repetition rate

– Termination character detection for end of block identification

– Error detection (parity error, framing error)

• Extended Transparent Mode

– Fully bit transparent (no framing, no bit manipulation)

– Octet-aligned transmission and reception

• Protocol and Mode Independent

– Data bit inversion

– Data overflow and underrun detection

– Timer

Protocol Support

• Address Recognition Modes

– No address recognition (Address Mode 0)

– 8-bit (high byte) address recognition (Address Mode 1)

– 8-bit (low byte) or 16-bit (high and low byte) address recognition (Non Auto Mode)

• HDLC Auto Mode

– 8-bit or 16-bit address generation/recognition

– Support of LAPB/LAPD

– Automatic handling of S- and I-frames

– Automatic processing of control byte(s)

– Modulo-8 or modulo-128 operation

– Programmable time-out and retry conditions

– SDLC Normal Response Mode (NRM) operation for slave

Microprocessor Interface

• 33 MHz/32-bit PCI bus interface option.

• 33 MHz/32-bit De-multiplexed bus interface option.

• 8-channel DMA controller with buffer chaining capability.

– Master 15-word burst read and write capability (PCI Mode).

– Master 4-word burst read and write capability (DEMUX Mode).

– Slave single-word read and write capability.

• Circular interrupt queues with variable size.

• Maskable interrupts for each channel

Other Interfaces

• 8-/16-bit optional Local Bus Interface (LBI) for driving non-PCI peripherals in a PCI

environment.

• Synchronous Serial Control interface (SSC) for controlling peripherals.

• 16-bit General Purpose Port (GPP).

PEB20534 Datasheet(PDF) 21 Page - Infineon Technologies AG

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