M24512-DRE datasheet(19/41 Pages) STMICROELECTRONICS

No. de pieza	M24512-DRE

Descripción Electrónicos	512-Kbit serial IC bus EEPROM - 105C operation

PDF	41 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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19 / 41 page

DocID027240 Rev 1

19/41

M24512-DRE

Instructions

4.1.5

Minimizing Write delays by polling on ACK

The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC

parameters, but the typical time is shorter. To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in Figure 7, is:

•

Initial condition: a Write cycle is in progress.

•

Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

•

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 7. Write cycle polling flowchart using ACK

M24512-DRE Datasheet(PDF) 19 Page - STMicroelectronics