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SPEAR320S Datasheet(PDF) 10 Page - STMicroelectronics |
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SPEAR320S Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 113 page ![]() Description SPEAr320S 10/113 Doc ID 022508 Rev 2 Figure 1. SPEAr320S architectural block diagram JTAG Trace ETM I/F CPU Subsystem Lowspeed connectivity Serial Flash I/F Memory interfaces 32 KB BootROM DDR2/LPDDR Ctrl CAN (2x) UART (7x) Debug I/F 8 KB St ti RAM MMU ARM9EJS Core 16 KB ICache 16 KB DCache HMI features SSP (3x) Static Memory Ctrl External Memory I/F RS485 I2C (3x) Static RAM DisplayCtrl JPEG Codec I2S Audio I/F Fast IrDA SPP ADC Config Regs BusInterfaces USB 2 0 Host (2x) Highspeed connectivity GPIO XGPIO Reset & clock System Controller Config Regs (MISC) VectoredInterrupt Controller Watchdog Touchscreen I/F USB 2.0 Host (2x) USB 2.0 Device DMA Ctrl Cryptographic Coprocessor Generator Timers (6x) PWM (4x) Fast Ethernet (2x) BUSMATRIXInterconnect Opt. Battery SDIO/MMC RTC |
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