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LAN9730 Datasheet(PDF) 13 Page - Microchip Technology |
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LAN9730 Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 222 page ![]() 2012-2015 Microchip Technology Inc. DS00001946A-page 13 LAN9730/LAN9730i 1 Transmit Clock (Internal PHY Mode) TXCLK IS/O8 (PU) In Internal PHY Mode, this pin can be configured to display the respective internal MII signal. Refer to the Internal MII Visibility Enable (IME) bit of the Hardware Configuration Register (HW_CFG) on page 125 for additional information. Transmit Clock (External PHY Mode) TXCLK IS (PU) In External PHY Mode, this pin is the transmitter clock input from the external PHY. 1 Carrier Sense (Internal PHY Mode) CRS IS/O8 (PU) In Internal PHY Mode, this pin can be configured to display the respective internal MII signal. Refer to the Internal MII Visibility Enable (IME) bit of the Hardware Configuration Register (HW_CFG) on page 125 for additional information. Carrier Sense (External PHY Mode) CRS IS (PD) In External PHY Mode, the signal on this pin is input from the external PHY and indicates a net- work carrier. General Pur- pose I/O 3 (Internal PHY Mode Only) GPIO3 IS/O8/ OD8 (PU) This General Purpose I/O pin is fully programma- ble as either a push-pull output, an open-drain output or a Schmitt-triggered input. 1 MII Collision Detect (Internal PHY Mode) COL IS/O8 (PU) In Internal PHY Mode, this pin can be configured to display the respective internal MII signal. Refer to the Internal MII Visibility Enable (IME) bit of the Hardware Configuration Register (HW_CFG) on page 125 for additional information. MII Collision Detect (External PHY Mode) COL IS (PD) In External PHY Mode, the signal on this pin is input from the external PHY and indicates a colli- sion event. General Pur- pose I/O 0 (Internal PHY Mode Only) GPIO0 IS/O8/ OD8 (PU) This General Purpose I/O pin is fully programma- ble as either a push-pull output, an open-drain output or a Schmitt-triggered input. Note: This pin may be used to signal PME when Internal PHY and PME Modes of operation are in effect. Refer to Chapter 5.0, "PME Operation" for additional information. TABLE 2-1: MII INTERFACE PINS (CONTINUED) Num Pins Name Symbol Buffer Type Description |
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