TAS5731MPHPR datasheet(46/81 Pages) TI1

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TAS5731M

SLOS838C – JULY 2013 – REVISED AUGUST 2015

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9.6.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5731M. The clock control register contains

the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The

device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of

192 fS and 384 fS only.

Table 4. Clock Control Register (0x00)

FUNCTION

–

fS = 32-kHz sample rate

–

Reserved(1)

–

Reserved(1)

–

fS = 44.1/48-kHz sample rate

(2)

–

fS = 16-kHz sample rate

–

fS = 22.05/24-kHz sample rate

–

fS = 8-kHz sample rate

–

fS = 11.025/12-kHz sample rate

–

MCLK frequency = 64 × fS

(3)

–

MCLK frequency = 128 × fS

(3)

–

MCLK frequency = 192 × fS

(4)

–

MCLK frequency = 256 × fS

(2) (5)

–

MCLK frequency = 384 × fS

–

MCLK frequency = 512 × fS

–

Reserved(1)

–

Reserved(1)

–

Reserved(1) (2)

–

Reserved(1) (2)

(1)

Reserved registers must not be accessed.

(2)

Default values are in bold.

(3)

Only available for 44.1-kHz and 48-kHz rates

(4)

Rate only available for 32/44.1/48-kHz sample rates

(5)

Not available at 8 kHz

9.6.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision.

Table 5. General Status Register (0x01)

FUNCTION

Identification code

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