FXLS8471Q datasheet(39/75 Pages) FREESCALE

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FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

10.2

Auto-Sleep trigger

10.2.1

ASLP_COUNT (0x29) register

The ASLP_COUNT register sets the minimum time period of event flag inactivity required to initiate a change from the current

active mode ODR value specified in CTRL_REG1[dr] to the Sleep mode ODR value specified in CTRL_REG1[aslp_rate],

provided that CTRL_REG2[slpe] = 1.

See Table 45 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event.

If the fifo_gate bit is set to logic ‘1’, the assertion of the SRC_ASLP interrupt does not prevent the system from transitioning to Sleep or from Wake mode; instead

it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer.

The interrupt sources listed in Table 45 affect the auto-sleep, return to sleep and wake from sleep mechanism only if they have

been previously enabled. The functional block event flags that are bypassed while the system is in Auto-Sleep mode are

temporary disabled (see Section 10.1.10, “CTRL_REG3 [Interrupt Control Register] (0x2C) register,” on page 35 for more

information) and are automatically re-enabled when the device returns from Auto-Sleep mode (that is, wakes up), except for the

data ready function.

If any of the interrupt sources listed under the Return-to-Sleep column is asserted before the sleep counter reaches the value

specified in ASLP_COUNT, then all sleep mode transitions are terminated and the internal sleep counter is reset. If none of the

interrupts listed under the Return-to-Sleep column are asserted within the time limit specified by the ASLP_COUNT register, the

system will transition to the Sleep mode and use the ODR value specified in CTRL_REG1[aslp_rate].

Table 42. ASLP_COUNT register

aslp_cnt[7:0]

8’b00000000

Table 43. ASLP_COUNT bit description

Field

Description

aslp_cnt[7:0]

See Table 44 for details

Table 44. ASLP_COUNT relationship with ODR

Output Data Rate (ODR)

Maximum inactivity time (s)

ODR time step (ms)

ASLP_COUNT step (ms)

800

1.25

320

400

2.5

320

200

320

100

320

12.5

320

6.25

160

320

1.56

640

Table 45. Sleep/Wake mode gates and triggers

Interrupt source

Event restarts time and

delays Return-to-Sleep

Event will Wake-from-Sleep

SRC_FIFO

Yes

SRC_TRANS

Yes

SRC_LNDPRT

Yes

SRC_PULSE

Yes

SRC_FFMT

Yes

SRC_ASLP

No*

SRC_AVECM

Yes

FXLS8471Q Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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