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100331 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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100331 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 8 page ![]() 100331 Low Power Triple D Flip-Flop General Description The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Com- mon Clock (CP C), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CP n), Direct Set (SD n) and Direct Clear (CDn) inputs. Data enters a mas- ter when both CP n and CPC are LOW and transfers to a slave when CP n or CPC (or both) go HIGH. The Master Set, Master Reset and individual CD n and SDn inputs override the Clock inputs. All inputs have 50 k Ω pull-down resistors. Features n 35% power reduction of the 100131 n 2000V ESD protection n Pin/function compatible with 100131 n Voltage compensated operating range = −4.2V to −5.7V n Available to industrial grade temperature range n Available to Standard Microcircuit Drawing (SMD) 5962-9153601 Logic Symbol Pin Names Description CP 0–CP2 Individual Clock Inputs CP C Common Clock Input D 0–D2 Data Inputs CD 0–CD2 Individual Direct Clear Inputs SD n Individual Direct Set Inputs MR Master Reset Input MS Master Set Input Q 0-Q2 Data Outputs Q 0–Q2 Complementary Data Outputs Connection Diagrams DS100300-1 24-Pin DIP DS100300-2 24-Pin Quad Cerpak DS100300-3 August 1998 © 1998 National Semiconductor Corporation DS100300 www.national.com |
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