SM8580AM

NIPPON PRECISION CIRCUITS—21

Periodic interrupt mode (TI/TP = 1)

When TIE is 1 and a timer interrupt event occurs (TF bit is set to 1), TIRQN goes LOW. If TIE is 0, however,

TIRQN is in a high-impedance state, and the TF bit remains set to 1.

quency set by register D in bank 1 bits FD3 and FD4.

Source clock

4096Hz

0.122ms

64Hz

7.81ms

1 H z

7.81ms

1/60Hz

7.81ms

TIE bit

TIRQN pin

TF bit

"0"

"1"

"0"

"1"

Auto-return

Setting TF bit to "0".

Interrupt is active.

Hi-Z

"L" level

Source CLK

Auto return time (

TIRQN pin

Interrupt cycle

"0"

Hi-Z