SM5847AF

NIPPON PRECISION CIRCUITS—23

*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.

Figure 8. LR alternating, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = L, 24-bit

*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.

Figure 9. LR simultaneous, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = H, 24-bit

LRCI

1 / fs

Lch

Rch

*1

1

24

1

24

BCKI

IW1N/DIL

MSB

LSB

MSB

LSB

IW2N/DIR

Don't care

Don't care

Don't care

Don't care

BCKI

LRCI

IW1N/DIL

IW2N/DIR

MSB

MSB

LSB

LSB

1 / fs

* 1

1

24

Don't care

Don't care