MT88L89

Advance Information

4-134

Table 3. Internal Register Functions

Table 4. CRA Bit Positions

Table 5. CRB Bit Positions

Motorola

Intel

RS0

R/W

WR

RD

FUNCTION

00

0

1

Write to Transmit

Data Register

01

1

0

Read from Receive

Data Register

10

0

1

Write to Control Register

11

1

0

Read from Status Register

b3

b2

b1

b0

RSEL

IRQ

CP/DTMF

TOUT

b3

b2

b1

b0

C/R

S/D

TEST

BURST

ENABLE

Table 6. Control Register A Description

BIT

NAME

DESCRIPTION

b0

TOUT

Tone Output Control. A logic high enables the tone output; a logic low turns the tone output

off. This bit controls all transmit tone functions.

b1

CP/DTMF

Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;

a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and

transmitting DTMF signals. In CP mode a retangular wave representation of the received

tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control

register A, b2=1).

In order to be detected, CP signals must be within the bandwidth

specified in the AC Electrical Characteristics for Call Progress.

Note: DTMF signals cannot be detected when CP mode is selected.

b2

IRQ

Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the

interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,

b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been

received for a valid guard time duration, or 2) the transmitter is ready for more data (burst

mode only).

b3

RSEL

Register Select. A logic high selects control register B for the next write cycle to the

control register address. After writing to control register B, the following control register

write cycle will be directed to control register A.