ASM705CSA datasheet(3/13 Pages) ONSEMI

3 / 13 page

ASM705, ASM706, ASM707, ASM708, ASM813L

http://onsemi.com

Table 1. PIN DESCRIPTION

Pin Number

ASM705/706

ASM707/708

ASM813L

DIP/

MicroSO

DIP/

MicroSO

DIP/

MicroSO

Name

Function

Manual reset input. The active LOW input triggers a

reset pulse. A 250 mA pull−up current allows the pin

to be driven by TTL/CMOS logic or shorted to

ground with a switch.

VCC

+5 V power supply input.

GND

Ground reference for all signals.

PFI

Power−fail input voltage monitor. With PFI less than

1.25 V, PFO goes LOW. Connect PFI to Ground or

VCC when not in use.

PFO

Power−fail output. The output is active LOW and

sinks current when PFI is less than 1.25 V.

−

WDI

Watchdog input. WDI controls the internal watchdog

timer. A HIGH or LOW signal for 1.6 sec at WDI

allows the internal timer to run−out, setting WDO

LOW. The watchdog function is disabled by floating

WDI or by connecting WDI to a high impedance

three−state buffer. The internal watchdog timer

clears when: RESET is asserted; WDI is three−

stated; or WDI sees a rising or falling edge.

−

Not Connected.

−

RESET

Active LOW reset output. Pulses LOW for 200 ms

when triggered, and stays LOW whenever VCC is

below the reset threshold. RESET remains LOW for

200 ms after VCC rises above the reset threshold or

MR goes from LOW to HIGH. A watchdog timeout

will not trigger RESET unless WDO is connected to

MR.

−

WDO

Watchdog output. WDO goes LOW when the 1.6

second internal watchdog timer times−out and does

not go HIGH until the watchdog is cleared. In addi-

tion, when VCC falls below the reset threshold,

WDO goes LOW. Unlike RESET, WDO does not

have a minimum pulse width and as soon as VCC

exceeds the reset threshold, WDO goes HIGH with

no delay.

−

RESET

Active HIGH reset output. The inverse of RESET.

The ASM813L only has a RESET output.

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