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GP2021 Datasheet(PDF) 20 Page - Mitel Networks Corporation |
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GP2021 Datasheet(HTML) 20 Page - Mitel Networks Corporation |
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20 / 62 page ![]() 20 GP2021 Fig.19 Correlator write and read cycles 20MHz INTERNAL CLOCK MCLK ARM_ALE DBE NRW INTERNAL WRITE INTERNAL READ A<22:20>, A<9:0> D<15:0> VALID VALID NOTE: NBW is High and NMREQ Low VALID Debug (Abort) Function This is a feature designed to aid debugging and functions as follows:– In ARM System Mode, the MULTI_FN_IO pin can be configured as a TRIGGER input to the Debug block via the IO_CONFIG register (see Detailed Description of Registers). In this mode a rising edge at the MULTI_FN_IO pin will generate a valid ARM data Abort sequence at the ABORT pin as shown in Fig. 20. Standard Interface Mode This mode allows the GP2021 to be interfaced to most standard 16 and 32 bit microprocessors as shown in Fig. 21. No memory control is provided, so external glue logic may be required in order to interface the microprocessor to memory. ABORT MCLK MULTI_FN_IO NOPC NMREQ Fig.20 Debug (Abort) Function |
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