LX1668

PRODUCT DA T ABOOK 1996/1997

7

Copyright © 1999

Rev. 1.0

4/99

THEOR Y OF OPERA TION

SWITCHER OUTPUT VOLTAGE REGULATION

Refer to the IC Block Diagram and the Product Highlight circuit.

When the top MOSFET turns ON, the inductor current increases.

The voltage at V

capacitor and the current-sensing resistor. When the V

voltage reaches the threshold voltage of the error comparator,

V

PWM latch is reset. Consequently, the top MOSFET turns OFF

and the bottom (synchronous) MOSFET turns ON. The off-time

control block controls the off-time of the top MOSFET. During

the off-time, the inductor current and the V

FB

pin voltage

decrease. As the off-time finishes, the synchronous MOSFET

turns OFF and the top MOSFET turns ON again, repeating the

previous cycle. A break-before-make circuit prevents simulta-

neous conduction of the two MOSFET’s.

The 40mV offset to the set voltage enhances the transient

response of the output voltage, as shown in Figure 4 below.

s The peak voltage at the V

voltage and its average is the peak voltage minus the ripple

voltage at V

s The output voltage is the voltage at the V

voltage drop across the current sensing resistor (I * R

s At light loads, the voltage drop across the sensing resistor

is small; hence, the output voltage is approximately the

voltage at the V

set voltage, V

s At heavy loads, larger current flows in the sense resistor,

therefore, the voltage drop is higher and the output voltage

is lower.

This adaptive positioning of the output voltage as the load

changes allows a greater output voltage excursion during a fast

step-load transient and requires fewer output capacitors to meet

the transient-response specification.

POWER UP and INITIALIZATION

At power up, the LX1668 monitors the supply voltage to both the

+5V and the +12V pins (there is no special requirement for the

sequence of the two supplies). Before both supplies reach their

under-voltage lock-out (UVLO) thresholds, the soft-start (SS) pin

is held low to prevent soft-start from beginning; the off-time

control is disabled and the top MOSFET is kept OFF. The two

LDO regulators are designed not to over-voltage regardless of

supply voltages. After both supplies pass the UVLO thresholds,

the circuit begins soft-start.

SOFT-START

Once the supplies are above the UVLO threshold, the soft-start

capacitor begins to be charged up by the set voltage (DAC

output) through a 20k

Ω internal resistor. The capacitor voltage

at the SS pin rises as a simple RC circuit. The SS pin plus a 40mV

offset is connected to the error comparator’s non-inverting input

that controls the output peak voltage. The output voltage will

follow the SS pin voltage if sufficient charging current is provided

to the output capacitor.

The simple RC soft-start allows the output to rise faster at the

beginning and slower at the end of the soft-start interval. Thus,

the required charging current into the output capacitor is less at

the end of the soft-start interval so decreasing the possibility of

an over-current. A comparator monitors the SS pin voltage and

indicates the end of soft-start when SS pin voltage reaches 95%

of V

See Application Information section for further details.

FIGURE 4 — Adaptive Voltage Positioning

Adaptive voltage

positioning offset

V

Nominal set-point

voltage, V

Initial voltage drop is

mainly due to the product

of the load current step and

ESR of the capacitors.

∆V = ∆I * ESR

(ESL effects are ignored)

Steady state voltage at high

current is approximately

V

Output voltage

V

Output current transient

step,

∆I = 0 to 14A

(5A/Div)

Dynamic voltage tolerance

V

L