CMPWR025 datasheet(7/8 Pages) ONSEMI

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CMPWR025

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turned off, due to power supply inductance. This has no

effect on the output voltage.

Figure 7. VCC1 Rising form 0 V to 5 V, VCC2 = 5 V.

Ch1 and Ch2: VCC1 and VCC2, offset = 5 V.

Ch3: VOUT, offset = 5 V.

VCC1 Falling from 5 V to 0 V (VCC2 = 5 V). Figure 8

shows the primary supply VCC1 becoming deselected during

a 5 V to 0 V transition. The test conditions are the same as

in Figure 7. Channel 2 switch is turned on as soon as VCC2

and VCC1 are about 200 mV. A negative glitch appears on

VCC2, when channel 2 is turned on. This has no effect on the

output voltage.

Figure 8. VCC1 Falling form 0 V to 5 V (VCC2 = 5 V).

Ch1 and Ch2: VCC1 and VCC2, offset = 5 V.

Ch3: VOUT, offset = 5 V.

VCC1 Rising (VCC2 = 5 V). Figure 9 is a bad test set−up

that shows what may happen if either power supply source

resistance RS1 or RS2 is too large. In this example, RS2 is

increased to 0.3

Figure 9. VCC1 Rising (VCC2@ = 5 V).

Ch1 and Ch2: VCC1 and VCC2@, offset = 5 V.

Ch3: VOUT, offset = 3.3 V.

The oscillation during the power transition is caused by

the cumulative voltage change across RS1 and RS2 being

greater than the hysteresis. The behavior is exacerbated by:

 a high load current,

 too many parasitics on power lines, and

 noisy power sources.

To avoid such behavior, the solution is to reduce the load

or parasitic capacitance on power supply and layout, or use

a more stable power supply.

Parallel Operation

Two CMPWR025 devices may be symmetrically ganged

in parallel to increase total current capacity. Careful

attention must be paid to minimizing series resistance and

PCB parasitics during layout, both between the dual

CMPWR025’s inputs and also between the supplies and the

devices, as described above.

In a well designed layout, a pair of CMPWR025’s can

provide an output approaching twice that of a single device.

See Application Note AP−211 for more information.

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