ML6460CS datasheet(10/30 Pages) MICRO-LINEAR

10 / 30 page

ML6460

FIELD (1,2 and 3,4)

FIELD (ODD/EVEN)

ANALOG FIELDS 1 & 2

ANALOG FIELDS 3 & 4

ANALOG FIELDS 1 & 2

ODD

EVEN

ODD

EVEN

ODD

EVEN

Figure 2a. FIELD Pin Output Summary

active edge of HSYNC

HSYNC

VSYNC

coincident interval

for HRESET_MODE=0

64 pixels

–32 pixels

active edge of HSYNC

HSYNC

VSYNC

coincident interval

for HRESET_MODE=1

64 pixels

active edge of VSYNC

Figure 3. Coincident Valid Sync Intervals for External Slave Mode

PIXEL SYNCHRONIZATION

Master Mode

In this mode, the active edge of horizontal sync pulse

through the HSYNC pin (configured as an output)

indicates the beginning of an active video line (or the

beginning of the horizontal blanking) and the

multiplexed YCrCb pixel data must be synchronized to

this edge for proper video location, as well as the proper

demultiplexing of YCrCb values. This synchronization, as

shown in Figures 4 through 5a, is controlled by

SEL_HSYNC1 (B14) and SEL_HSYNC0 (B13). Figures 4

and 4a show synchronization for active edge at the

beginning of active video for positive or negative HSYNC

polarity while Figures 5 and 5a show synchronization for

active edge at the beginning of horizontal blanking for

positive or negative HSYNC polarity.

FUNCTIONAL DESCRIPTION (Continued)

ML6460CS Datasheet(PDF) 10 Page - Micro Linear Corporation

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