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ML6421 Datasheet(PDF) 8 Page - Micro Linear Corporation

No. de pieza ML6421
Descripción Electrónicos  Triple Phase and Sinx/x Equalized, Low-Pass Video Filter
PDF  13 Pages
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Fabricante Electrónico  MICRO-LINEAR [Micro Linear Corporation]
Página de inicio  http://www.microlinear.com
Logo MICRO-LINEAR - Micro Linear Corporation

ML6421 Datasheet(HTML) 8 Page - Micro Linear Corporation

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ML6421
8
FUNCTIONAL DESCRIPTION
The ML6421 single-chip Triple Video Filter IC is intended
for consumer and low cost professional video
applications. Each of the three channels incorporates an
input buffer amplifier, a sixth order lowpass filter, a first
order allpass equalizer, Sinx/x equalizer and an output
amplifier capable of driving 75
Ω to ground.
The ML6421 can be driven by a DAC with Range down to
0V. When Range is low the input and output signal range
is 0.5V to 2.5V. When the input signal includes 0V, Range
should be tied high. In this case, an offset is added to the
input so that the output swing is kept between 0.5V to
2.5V. The output amplifier is capable of driving up to
24mA of peak current; therefore the output voltage should
not exceed 1.8V when driving 75
Ω to ground.
APPLICATION GUIDELINES
OUTPUT CONSIDERATIONS
The triple filters have unity gain. The circuit has unity
gain (0dB) when connected to a 150
Ω load, and a –6dB
gain when driving a 75
Ω load via a 75Ω series output
resistor. The output may be either AC or DC coupled. For
AC coupling, the –3dB point should be 5Hz or less. There
must also be a DC path of -500
Ω to ground for output
biasing.
INPUT CONSIDERATIONS
The input resistance is 4k
Ω. The input may be either DC or
AC coupled. (Note that each input sources 80 to 125µA of
bias current). The ML6421 is designed to be directly
driven by a DAC. For current output video DACs, a 75
Ω or
150
Ω resistor to ground may need to be added to the DAC
output (filter input).
Figure 9. ML6421 AC Coupled DC Bias Test Circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VINB
VINA
RANGE
GNDA
GND
VCCA
VOUTA
VOUTB
GNDB
VINC
GND
GNDC
VCC
VCCC
VOUTC
VCCB
75
75
OUTA
OUTB
1
µF
0.1
µF
0.1
µF
100
µF
100
µF
3.1k
47
1k
85
47
85
3.1k
1k
INB
INA
0.1
µF
100
µF
1nF
1nF
1nF
1nF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.001
µF
1
µF
100
µF
75
85
47
OUTC
3.1k
1k
INC
+5V
FB2
FB1
DC
BIAS
INPUT SIGNAL = 2VP-P
INPUT
DECOUPLING
SUPPLY NOISE
CLAMPING
INPUT
TERMINATION
1
µF



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