PIC16C71 datasheet(12/176 Pages) MICROCHIP

12 / 176 page

PIC16C71X

DS30272A-page 12

4.2

Data Memory Organization

The data memory is partitioned into two Banks which

contain the General Purpose Registers and the Special

Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1

→ Bank 1

RP0 (STATUS<5>) = 0

→ Bank 0

Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers implemented as

static RAM. Both Bank 0 and Bank 1 contain special

function registers. Some "high use" special function

registers from Bank 0 are mirrored in Bank 1 for code

reduction and quicker access.

4.2.1

GENERAL PURPOSE REGISTER FILE

The register ﬁle can be accessed either directly, or indi-

rectly

through

the

File

Select

FSR

(Section 4.5).

FIGURE 4-4:

PIC16C710/71 REGISTER FILE

MAP

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

ADRES

ADCON0

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

ADCON1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

General

Purpose

7Fh

FFh

Bank 0

Bank 1

File

Address

ADRES

2Fh

30h

AFh

B0h

File

Address

General

Purpose

Mapped

in Bank 0(3)

PCON(2)

Unimplemented data memory locations, read

as '0'.

Note 1:

Not a physical register.

The PCON register is not implemented on the

PIC16C71.

These locations are unimplemented in Bank 1.

Any access to these locations will access the

corresponding Bank 0 register.

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