© 1996 Microchip Technology Inc.

DS21127B-page 3

24LCS21

TABLE 1-3:

AC CHARACTERISTICS

Parameter

Symbol

Vcc= 2.5-5.5V

Vcc= 4.5 - 5.5V

Units

Remarks

Min

Max

Min

Max

Clock frequency

0

100

0

400

kHz

Clock high time

4000

—

600

—

ns

Clock low time

4700

—

1300

—

ns

SDA and SCL rise time

—

1000

—

300

ns

(Note 1)

SDA and SCL fall time

—

300

—

300

ns

(Note 1)

START condition hold time

4000

—

600

—

ns

After this period the first clock

pulse is generated

START condition setup time

4700

—

600

—

ns

Only relevant for repeated

START condition

Data input hold time

0

—

0

—

ns

(Note 2)

Data input setup time

250

—

100

—

ns

STOP condition setup time

4000

—

600

—

ns

Output valid from clock

—

3500

—

900

ns

(Note 2)

Bus free time

4700

—

1300

—

ns

Time the bus must be free

before a new transmission can

start

—

250

20 + 0.1

250

ns

≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

—

100

—

50

ns

(Note 3)

Write cycle time

—

10

—

10

ms

Byte or Page mode

Transmit-Only Mode Parameters

Output valid from VCLK

—

2000

—

1000

ns

VCLK high time

4000

—

600

—

ns

VCLK low time

4700

—

1300

—

ns

VCLK setup time

0—

0

—

ns

VCLK hold time

4000

—

600

—

ns

Mode transition time

—

500

—

500

ns

Transmit-Only power up time

0—

0

—

ns

Input filter spike suppression

(VCLK pin)

—

100

—

100

ns

Endurance

—

10M

—

10M

—

cycles

25

(Note 4)

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.