24LC08B/16B MODULES

DS21224A-page 4

© 1997 Microchip Technology Inc.

2.0

PAD DESCRIPTIONS

2.1

SDA (Serial Data)

This is a Bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

Ω).

For normal data transfer SDA is allowed to change only

during SCL low.

Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

2.2

SCL (Serial Clock)

This input is used to synchronize the data transfer from

and to the device.

3.0

FUNCTIONAL DESCRIPTION

The 24LC08B/16B supports a Bi-directional 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24LC08B/16B works as slave. Both, master and slave

can operate as transmitter or receiver but the master

device determines which mode is activated.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 5-2).

4.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

4.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwrite does occur it will replace data in a first in first

out fashion.