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PUSB3FR4 Datasheet(PDF) 3 Page - NXP Semiconductors |
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PUSB3FR4 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 15 page ![]() PUSB3FR4 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1 — 26 January 2015 3 of 15 NXP Semiconductors PUSB3FR4 ESD protection for ultra high-speed interfaces 6. Characteristics [1] This parameter is guaranteed by design. [2] According to IEC 61000-4-5 (8/20 s current waveform). [3] 100 ns Transmission Line Pulse (TLP); 50 ; pulser at 80 ns. Table 5. Characteristics Tamb =25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VBR breakdown voltage II =1 mA 5.5 9 - V ILR reverse leakage current per channel; VI =5V - <1 100 nA VF forward voltage II = 1 mA -0.7 -V Cline line capacitance f = 1 MHz; VI =1.5 V [1] - 0.29 0.34 pF C line line capacitance difference f=1MHz; VI =1.5 V [1] - 0.02 0.05 pF rdyn dynamic resistance TLP [3] positive transient - 0.27 - negative transient - 0.27 - Vsbck snapback voltage II = 1 A; TLP 100/10 ns - 1.5 - V VCL clamping voltage IPP = 5 A; positive transient [2] -3 -V IPP = 5A; negative transient [2] - 3- V |
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