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74HC_HCT4053

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Product data sheet

Rev. 8 — 19 July 2012

5 of 32

NXP Semiconductors

74HC4053; 74HCT4053

Triple 2-channel analog multiplexer/demultiplexer

6.2 Pin description

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

Limiting values

[1]

To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional

switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case

there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.

[2]

For DIP16 packages: above 70

C the value of P

tot derates linearly with 12 mW/K.

Table 2.

Pin description

Symbol

Description

enable input (active LOW)

VEE

supply voltage

GND

ground supply voltage

S1, S2, S3

11, 10, 9

select input

1Y0, 2Y0, 3Y0

12, 2, 5

independent input or output

1Y1, 2Y1, 3Y1

13, 1, 3

independent input or output

1Z, 2Z, 3Z

14, 15, 4

common output or input

VCC

supply voltage

Table 3.

Function table [1]

Inputs

Channel on

LLnY0 to nZ

nY1 to nZ

switches off

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

[1]

0.5

+11.0

IIK

input clamping current

VI < 0.5 V or VI >VCC +0.5 V

20

ISK

switch clamping current

VSW < 0.5 V or VSW >VCC +0.5 V

20

ISW

switch current

0.5 V < V

SW <VCC +0.5 V

25

IEE

supply current

20

ICC

supply current

IGND

ground current

50

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

DIP16 package

[2] -

750

SO16, (T)SSOP16, and

DHVQFN16 package

[3] -

500

power dissipation

per switch

100

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