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DS121024

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

SPA2118Z

Simplified Device Schematic

Recommended Land Pattern

Dimensions in inches (millimeters)

Refer to drawing posted at www.rfmd.com for tolerances.

Pin

Function

Description

1VC1

Supply voltage for the first stage transistor. The configuration as shown on the application schematic is required for opti-

mum RF performance.

2VBIAS

Bias control pin for the active bias network. Recommended configuration is shown in the application schematic.

3RF IN

RF input pin. This pin requires the use of an external DC-blocking capacitor as shown in the application shcematic.

4VPC2

Bias control pin for the active bias network for the second stage. The recommended configuration is shown in the appli-

cation schematic.

5, 6,

7, 8

on this pin a DC-blocking capacitor should be used in most applications. (See application schematic.) The supply side of

the bias network should be well bypassed. An output matching network is necessary for optimum performance.

EPAD

GND

Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for thermal and

RF performance. Several vias should be located under the EPAD as shown in the recommended land pattern.

2

3

5-8

ACTIVE BIAS

NETWORK

ACTIVE BIAS

NETWORK

2

4

1

(

r

e

t

e

m

a

r

a

P

0.020 [0.51]

0.140 [3.56]

0.080 [2.03]

0.050 [1.27]

0.150 [3.81]

0.300 [7.62]

Plated-Thru Holes

(0.015" Dia, 0.030" Pitch)

Machine

Screws