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UPD78323LP Datasheet(PDF) 39 Page - NEC |
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UPD78323LP Datasheet(HTML) 39 Page - NEC |
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39 / 86 page ![]() BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT 8 SBIC SET CLEAR D SO Latch Q Busy/ Acknowledge Detector Shift Register SIO Internal Bus MOD0 CLS0 CLS1 MOD1 WUP CRXE CTXE MOD2 CSIM 8 SI/SB1 SO/SB0 N-ch Open Drain Output Enable SCK Bus Release/ Command/Acknowledge Detector Serial Clock Counter Serial Clock Controller Interrupt Signal Generation Controller INTCSI MPX CLS1 CLS0 Baud Rate Generator Output fCLK/8 fCLK/32 Figure 3-7. Block Diagram of Clock Synchronous Serial Interface |
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