5

LTC2420

(Pin 4) with a 10

µF tantalum capacitor in parallel with

0.1

µF ceramic capacitor as close to the part as possible.

voltage range may be limited by the pin absolute maxi-

GND (Pin 4): Ground. Shared pin for analog ground,

digital ground, reference ground and signal ground. Should

be connected directly to a ground plane through a mini-

mum length trace or it should be the single-point-ground

in a single point grounding system.

CS (Pin 5): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion, the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW on CS wakes up the ADC. A

LOW-to-HIGH transition on this pin disables the SDO

digital output. A LOW-to-HIGH transition on CS during the

Data Output transfer aborts the data transfer and starts a

new conversion.

SDO (Pin 6): Three-State Digital Output. During the data

output period this pin is used for serial data output. When

high impedance state. During the Conversion and Sleep

periods, this pin can be used as a conversion status out-

put. The conversion status can be observed by pulling CS

LOW.

SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as digital output

for the internal serial interface clock during the data output

period. In External Serial Clock Operation mode, SCK is

used as digital input for the external serial interface. A

weak internal pull-up is automatically activated in Internal

Serial Clock Operation mode. The Serial Clock mode is

determined by the level applied to SCK at power up and the

falling edge of CS.

controls the ADC’s notch frequencies and conversion

converter uses its internal oscillator and the digital filter’s

the converter uses this signal as its clock and the digital

APPLICATIO S I FOR ATIO

The LTC2420 is pin compatible with the LTC2400. The two

devices are designed to allow the user to incorporate

either device in the same design with no modifications.

While the LTC2420 output word length is 24 bits (as

opposed to the 32-bit output of the LTC2400), its output

clock timing can be identical to the LTC2400. As shown in

Figure 1, the LTC2420 data output is concluded on the

falling edge of the 24th serial clock (SCK). In order to

maintain drop-in compatibility with the LTC2400, it is

possible to clock the LTC2420 with an additional 8 serial

clock pulses. This results in 8 additional output bits which

are always logic HIGH.

Output Data Format

The LTC2420 serial output data stream is 24 bits long. The

first 4 bits represent status information indicating the

sign, input range and conversion state. The next 20 bits are

the conversion result, MSB first.

Bit 23 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is

always LOW.