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LTC2401IMS Datasheet(PDF) 7 Page - Linear Technology |
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LTC2401IMS Datasheet(HTML) 7 Page - Linear Technology |
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7 / 12 page  7 LTC2401/LTC2402 APPLICATIO S I FOR ATIO falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the VIN pin is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from – 0.125 • VREF to 1.125 • VREF. For input voltages greater than 1.125 • VREF, the conversion result is clamped to the value corresponding to 1.125 • VREF. For input voltages below – 0.125 • VREF, the conversion result is clamped to the value corresponding to – 0.125 • VREF. Single Ended Half-Bridge Digitizer with Reference and Ground Sensing Sensors convert real world phenomena (temperature, pressure, gas levels, etc.) into a voltage. Typically, this voltage is generated by passing an excitation current Table 2. LTC2401/LTC2402 Output Data Format Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 … Bit 4 Bit 3-0 Input Voltage EOC CH SELECT SIG EXR MSB LSB SUB LSBs* VIN > 9/8 • VREF 0 CH0/CH1 1100 0 11... 1 X 9/8 • VREF 0 CH0/CH1 1100 0 11... 1 X VREF + 1LSB 0 CH0/CH1 1100 0 00... 0 X VREF 0 CH0/CH1 1011 1 11... 1 X 3/4VREF + 1LSB 0 CH0/CH1 1011 0 00... 0 X 3/4VREF 0 CH0/CH1 1010 1 11... 1 X 1/2VREF + 1LSB 0 CH0/CH1 1010 0 00... 0 X 1/2VREF 0 CH0/CH1 1001 1 11... 1 X 1/4VREF + 1LSB 0 CH0/CH1 1001 0 00... 0 X 1/4VREF 0 CH0/CH1 1000 1 11... 1 X 0+/0– 0 CH0/CH1 1/0** 0 0 0 0 0 0 ... 0 X –1LSB 0 CH0/CH1 0111 1 11... 1 X –1/8 • VREF 0 CH0/CH1 0111 1 00... 0 X VIN < –1/8 • VREF 0 CH0/CH1 0111 1 00... 0 X *The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. **The sign bit changes state during the 0 code. VFULL-SCALE ERROR SENSOR SENSOR OUTPUT RP1 IEXCITATION + – VOFFSET ERROR + – + – RP2 24012 F02 Figure 2. Errors Due to Excitation Currents through the sensor. The wires connecting the sensor to the ADC form parasitic resistors RP1 and RP2. The excitation current also flows through parasitic resistors RP1 and RP2, as shown in Figure 2. The voltage drop across these parasitic resistors leads to systematic offset and full-scale errors. In order to eliminate the errors associated with these parasitic resistors, the LTC2401/LTC2402 include a full- scale set input (FSSET) and a zero-scale set input (ZSSET). As shown in Figure 3, the FSSET pin acts as a zero input full-scale sense input. Errors due to parasitic resis- tance RP1 in series with the half-bridge sensor are |
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