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PALCE20V8 Datasheet(PDF) 21 Page - Lattice Semiconductor

No. de pieza PALCE20V8
Descripción Electrónicos  EE CMOS 24-Pin Universal Programmable Array Logic
PDF  27 Pages
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Fabricante Electrónico  LATTICE [Lattice Semiconductor]
Página de inicio  http://www.latticesemi.com
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PALCE20V8 Datasheet(HTML) 21 Page - Lattice Semiconductor

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PALCE20V8 Family
21
ENDURANCE CHARACTERISTICS
The PALCE20V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.
ROBUSTNESS FEATURES
The PALCE20V8X-X/5 have some unique features that make them extremely robust, especially
when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins
cause unconnected pins to default to a known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely insensitive to any positive overshoot
that has a pulse width of less than about 100 ns for the /5 versions.
Symbol
Parameter
Test Conditions
Value
Unit
tDR
Min Pattern Data Retention Time
Max Storage Temperature
10
Years
Max Operating Temperature
20
Years
N
Max Reprogramming Cycles
Normal Programming Conditions
100
Cycles



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