Data Sheet S16434EJ1V0DS

11

µµµµPD16754

8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM

The output voltage is written to the LCD panel synchronized with the STB falling edge.

Figure 8

−−−−1. Output Circuit Block Diagram

SW1

Sn (Vx)

DAC

Output Amp.

−

+

SW1 switches according to the level of STB signal.

STB = L: SW = ON

STB = H: SW = OFF

Figure 8

−−−−2. Output Circuit Timing Chart

CLK

STB

SW1: OFF

Hi-Z

[1]

[1']

H is loaded with the rising edge of the next CLK [1’].

Latch operation of display data is completed with the falling edge of the next CLK which loaded STB = H.

Therefore, in order to complete latch operation of display data, it is necessary to input at least 2CLK in STB = H

period.